One type of memory device which has found wide commercial success in the electronics industry is commonly referred to as flash memory. This commercial success is due in part to the ability of flash memory devices to store electronic data over long periods of time without an electric power supply. In addition, flash memory devices can be erased and programmed by the end user after they are installed in an electronic device. This combined functionality is especially useful in electronic device applications, such as cellular telephones, personal digital assistants, and computer BIOS storage, and other applications where power supply is intermittent and programmability is desired.
Flash memory devices are made up of an array of individual memory transistors, or cells, which are similar to those used in other types of memory devices. Flash memory devices, however, typically achieve non-volatility of the memory cells by the addition of a floating gate between the control gate and the substrate region of the transistors. Like other memory devices, the transistors are oriented in rows and columns to form an array of transistors. As is common in the memory device art, the control gates of the memory cells in each row of the array are connected to a series of word lines, thus forming individual rows of cells that can be accessed by selecting the corresponding word line. Similarly, the drain regions of the cells in each column of the array are connected to a series of bit lines, thus forming individual columns of cells that can be accessed by selecting the corresponding bit lines. Finally, the source regions of each of the cells in the array are connected to a common source line. In some flash memory devices, the array of transistors is subdivided into sectors of separate transistor arrays to provide added flexibility to the programming and erasing operations.
The data stored in each memory cell represents a binary 1 or 0, as is well-known in the art. To perform a program, read, or erase operation on a particular cell in the array, various predetermined voltages are applied to the control gate, drain region, and source region of the memory cell. By applying these predetermined voltages to a particular bit line column, a particular word line row, and the common source line, an individual cell at the intersection of the bit line and word line can be selected for reading or programming.
To program a cell, the control gate and the drain region of the cell are raised to predetermined programming voltages and the source is grounded. The voltages on the control gate and the drain region cause the generation of hot electrons which are injected onto the floating gate where they become trapped, forming a negative charge on the floating gate. This electron transfer mechanism is often referred to as Channel Hot Electron (CHE) injection. When the programming voltages are removed, the negative charge on the floating gate is maintained, thereby raising the threshold voltage. The threshold voltage is used during reading operations to determine if the cell is in a charged state, that is programmed, or whether the cell is in an uncharged state, that is un-programmed.
Cells are read by applying a predetermined voltage to the control gate and the drain region and grounding the source of the cell. The current in the bit line is then sensed with a sense amplifier. If the cell is programmed, the threshold voltage will be relatively high and the bit line current will be zero or at least relatively low, thus registering a binary 0. On the other hand, if the cell is erased, the threshold voltage will be relatively low and the bit line current will be relatively high, thus registering a binary 1.
In contrast to the programming procedure, flash memory devices are typically bulk-erased by simultaneously erasing all the cells in a memory sector. One procedure for erasing an entire memory sector involves applying predetermined voltages to the common source line and all the word lines of the sector while the drain regions of the cells are left floating. This causes electron tunneling from the floating gate to the source region through Fowler-Nordheim (F-N) tunneling, which removes the negative charge from the floating gate of each of the cells in the memory sector.
Typically, the read operations are performed as a random access function, in which the user specifies a particular address in the memory array for the memory device to read. However, one function that can be provided in the memory device is a burst read mode. A burst read mode is an embedded function that sequentially reads the data in the entire memory array and outputs the data thus read to the user during succeeding clock cycles. In this mode, the user does not need to provide the cell addresses because a state machine in the memory device sequentially generates each cell address in the memory array. Generally, this function is useful when the user desires an output of all of the data in the memory device.
A number of important performance factors must be considered when designing a burst read mode, however. For example, flash memory devices are often used in hand held devices that provide a limited capacity power supply. Thus, the power consumption during the read function should be minimized. In addition, the speed of the burst read mode should be relatively fast so that the user can receive the entire output of the memory device without having to wait for the device. Another problem is that some circuits in the memory device can only operate correctly when the applied voltages are within a restricted range. Thus, the voltage must be strictly regulated to ensure proper functioning of the device.
There is a need for sense amplifier groups which correspond to the number of data words to be output successively at a burst read operation. Referring to FIG. 11 which shows a conventional column gate structure required for a burst read operation, four sense amplifier groups 10, 11, 12 and 13 and four column gate circuits 20, 21, 22 and 23 are needed to issue four data words. The column gate circuits 20-23 select columns (or bit lines) in response to corresponding column select signals Yset00-Yset03, Yset10-Yset13, Yset20-Yset23 and Yset30-Yset33.
To increase the number of data words to be read at a burst mode of operation to improve a burst read operation speed, additional sense amplifier groups and column select circuits are needed—in proportion to an increased data word number. As column select circuits are increased, column select signal groups are necessary in proportion thereto. This means that signal lines for transferring column select signals are increased in proportion to an increased data word number. For example, when reading out four data words at a burst mode of operation, 16 column select signal lines are required because four column select signals are applied for each column select circuit. Similarly, 32 column select signal lines are necessary when eight data words are read out at the burst mode of operation. To increase the number of data words that can be read, the size of a column select structure such as that shown in FIG. 11 must be increased, which increases the chip size.